# transfer IO 
set_property -dict {PACKAGE_PIN K28 IOSTANDARD LVCMOS25}  [get_ports io_systemclk]
set_property -dict {PACKAGE_PIN N25 IOSTANDARD LVCMOS25}  [get_ports io_systemRst]
set_property -dict {PACKAGE_PIN N30 IOSTANDARD LVCMOS25}  [get_ports io_cardio_card_group_cmd]
set_property -dict {PACKAGE_PIN N29 IOSTANDARD LVCMOS25}  [get_ports io_cardio_group_card_state]
set_property -dict {PACKAGE_PIN M27 IOSTANDARD LVCMOS25}  [get_ports {io_cardio_card_group_data[0]}]
set_property -dict {PACKAGE_PIN N27 IOSTANDARD LVCMOS25}  [get_ports {io_cardio_card_group_data[1]}]
set_property -dict {PACKAGE_PIN M30 IOSTANDARD LVCMOS25}  [get_ports {io_cardio_group_card_result[0]}]
set_property -dict {PACKAGE_PIN M29 IOSTANDARD LVCMOS25}  [get_ports {io_cardio_group_card_result[1]}]
set_property -dict {PACKAGE_PIN J26 IOSTANDARD LVCMOS25}  [get_ports {io_cardio_group_card_result[2]}]
set_property -dict {PACKAGE_PIN K26 IOSTANDARD LVCMOS25}  [get_ports {io_cardio_group_card_result[3]}]
set_property -dict {PACKAGE_PIN K30 IOSTANDARD LVCMOS25}  [get_ports {io_cardio_group_card_result[4]}]
set_property -dict {PACKAGE_PIN L30 IOSTANDARD LVCMOS25}  [get_ports {io_cardio_group_card_result[5]}]
set_property -dict {PACKAGE_PIN J28 IOSTANDARD LVCMOS25}  [get_ports {io_cardio_group_card_result[6]}]
set_property -dict {PACKAGE_PIN J27 IOSTANDARD LVCMOS25}  [get_ports {io_cardio_group_card_result[7]}]
create_clock -period 10.000 [get_ports io_systemclk]

# Daisy Chain
set_property -dict {PACKAGE_PIN J12 IOSTANDARD LVCMOS25} [get_ports {io_dcout_cim_dcdata[0]}]
set_property -dict {PACKAGE_PIN J11 IOSTANDARD LVCMOS25} [get_ports {io_dcout_cim_dcdata[1]}]
set_property -dict {PACKAGE_PIN G15 IOSTANDARD LVCMOS25} [get_ports {io_dcout_cim_dcdata[2]}]
set_property -dict {PACKAGE_PIN H15 IOSTANDARD LVCMOS25} [get_ports {io_dcout_cim_dcdata[3]}]
set_property -dict {PACKAGE_PIN K11 IOSTANDARD LVCMOS25} [get_ports {io_dcout_cim_dcvld}]
set_property -dict {PACKAGE_PIN L11 IOSTANDARD LVCMOS25} [get_ports {io_dcin_cim_dcdata[0]}]
set_property -dict {PACKAGE_PIN J14 IOSTANDARD LVCMOS25} [get_ports {io_dcin_cim_dcdata[1]}]
set_property -dict {PACKAGE_PIN K14 IOSTANDARD LVCMOS25} [get_ports {io_dcin_cim_dcdata[2]}]
set_property -dict {PACKAGE_PIN J13 IOSTANDARD LVCMOS25} [get_ports {io_dcin_cim_dcdata[3]}]
set_property -dict {PACKAGE_PIN K13 IOSTANDARD LVCMOS25} [get_ports {io_dcin_cim_dcvld}]

# chip0 IO bank15
set_property -dict {PACKAGE_PIN M28 IOSTANDARD LVCMOS25} [get_ports io_chipio_0_cim_fpga_clk]
set_property -dict {PACKAGE_PIN M23 IOSTANDARD LVCMOS25} [get_ports io_chipio_0_cim_fpga_state]
set_property -dict {PACKAGE_PIN M22 IOSTANDARD LVCMOS25} [get_ports io_chipio_0_fpga_cim_cmd]
set_property -dict {PACKAGE_PIN M25 IOSTANDARD LVCMOS25} [get_ports {io_chipio_0_fpga_cim_data[0]}]
set_property -dict {PACKAGE_PIN M24 IOSTANDARD LVCMOS25} [get_ports {io_chipio_0_fpga_cim_data[1]}]
set_property -dict {PACKAGE_PIN P22 IOSTANDARD LVCMOS25} [get_ports {io_chipio_0_cim_fpga_result[0]}]
set_property -dict {PACKAGE_PIN P21 IOSTANDARD LVCMOS25} [get_ports {io_chipio_0_cim_fpga_result[1]}]
set_property -dict {PACKAGE_PIN N24 IOSTANDARD LVCMOS25} [get_ports {io_chipio_0_cim_fpga_result[2]}]
set_property -dict {PACKAGE_PIN P23 IOSTANDARD LVCMOS25} [get_ports {io_chipio_0_cim_fpga_result[3]}]
set_property -dict {PACKAGE_PIN N22 IOSTANDARD LVCMOS25} [get_ports {io_chipio_0_cim_fpga_result[4]}]
set_property -dict {PACKAGE_PIN N21 IOSTANDARD LVCMOS25} [get_ports {io_chipio_0_cim_fpga_result[5]}]
set_property -dict {PACKAGE_PIN N20 IOSTANDARD LVCMOS25} [get_ports {io_chipio_0_cim_fpga_result[6]}]
set_property -dict {PACKAGE_PIN N19 IOSTANDARD LVCMOS25} [get_ports {io_chipio_0_cim_fpga_result[7]}]

# chip1 IO bank15
set_property -dict {PACKAGE_PIN L26 IOSTANDARD LVCMOS25} [get_ports  io_chipio_1_cim_fpga_clk]
set_property -dict {PACKAGE_PIN H29 IOSTANDARD LVCMOS25} [get_ports  io_chipio_1_cim_fpga_state]
set_property -dict {PACKAGE_PIN J29 IOSTANDARD LVCMOS25} [get_ports  io_chipio_1_fpga_cim_cmd]
set_property -dict {PACKAGE_PIN L20 IOSTANDARD LVCMOS25} [get_ports {io_chipio_1_fpga_cim_data[0]}]
set_property -dict {PACKAGE_PIN M20 IOSTANDARD LVCMOS25} [get_ports {io_chipio_1_fpga_cim_data[1]}]
set_property -dict {PACKAGE_PIN J22 IOSTANDARD LVCMOS25} [get_ports {io_chipio_1_cim_fpga_result[0]}]
set_property -dict {PACKAGE_PIN J21 IOSTANDARD LVCMOS25} [get_ports {io_chipio_1_cim_fpga_result[1]}]
set_property -dict {PACKAGE_PIN K21 IOSTANDARD LVCMOS25} [get_ports {io_chipio_1_cim_fpga_result[2]}]
set_property -dict {PACKAGE_PIN L21 IOSTANDARD LVCMOS25} [get_ports {io_chipio_1_cim_fpga_result[3]}]
set_property -dict {PACKAGE_PIN K24 IOSTANDARD LVCMOS25} [get_ports {io_chipio_1_cim_fpga_result[4]}]
set_property -dict {PACKAGE_PIN K23 IOSTANDARD LVCMOS25} [get_ports {io_chipio_1_cim_fpga_result[5]}]
set_property -dict {PACKAGE_PIN L23 IOSTANDARD LVCMOS25} [get_ports {io_chipio_1_cim_fpga_result[6]}]
set_property -dict {PACKAGE_PIN L22 IOSTANDARD LVCMOS25} [get_ports {io_chipio_1_cim_fpga_result[7]}]


# chip2 IO bank16
set_property -dict {PACKAGE_PIN E28 IOSTANDARD LVCMOS25} [get_ports  io_chipio_2_cim_fpga_clk]
set_property -dict {PACKAGE_PIN G30 IOSTANDARD LVCMOS25} [get_ports  io_chipio_2_cim_fpga_state]
set_property -dict {PACKAGE_PIN H30 IOSTANDARD LVCMOS25} [get_ports  io_chipio_2_fpga_cim_cmd]
set_property -dict {PACKAGE_PIN H27 IOSTANDARD LVCMOS25} [get_ports {io_chipio_2_fpga_cim_data[0]}]
set_property -dict {PACKAGE_PIN H26 IOSTANDARD LVCMOS25} [get_ports {io_chipio_2_fpga_cim_data[1]}]
set_property -dict {PACKAGE_PIN F30 IOSTANDARD LVCMOS25} [get_ports {io_chipio_2_cim_fpga_result[0]}]
set_property -dict {PACKAGE_PIN G29 IOSTANDARD LVCMOS25} [get_ports {io_chipio_2_cim_fpga_result[1]}]
set_property -dict {PACKAGE_PIN F27 IOSTANDARD LVCMOS25} [get_ports {io_chipio_2_cim_fpga_result[2]}]
set_property -dict {PACKAGE_PIN G27 IOSTANDARD LVCMOS25} [get_ports {io_chipio_2_cim_fpga_result[3]}]
set_property -dict {PACKAGE_PIN F28 IOSTANDARD LVCMOS25} [get_ports {io_chipio_2_cim_fpga_result[4]}]
set_property -dict {PACKAGE_PIN G28 IOSTANDARD LVCMOS25} [get_ports {io_chipio_2_cim_fpga_result[5]}]
set_property -dict {PACKAGE_PIN H25 IOSTANDARD LVCMOS25} [get_ports {io_chipio_2_cim_fpga_result[6]}]
set_property -dict {PACKAGE_PIN H24 IOSTANDARD LVCMOS25} [get_ports {io_chipio_2_cim_fpga_result[7]}]

# chip3 IO bank16
set_property -dict {PACKAGE_PIN D27 IOSTANDARD LVCMOS25} [get_ports  io_chipio_3_cim_fpga_clk]
set_property -dict {PACKAGE_PIN A26 IOSTANDARD LVCMOS25} [get_ports  io_chipio_3_cim_fpga_state]
set_property -dict {PACKAGE_PIN A25 IOSTANDARD LVCMOS25} [get_ports  io_chipio_3_fpga_cim_cmd]
set_property -dict {PACKAGE_PIN A28 IOSTANDARD LVCMOS25} [get_ports {io_chipio_3_fpga_cim_data[0]}]
set_property -dict {PACKAGE_PIN B28 IOSTANDARD LVCMOS25} [get_ports {io_chipio_3_fpga_cim_data[1]}]
set_property -dict {PACKAGE_PIN E30 IOSTANDARD LVCMOS25} [get_ports {io_chipio_3_cim_fpga_result[0]}]
set_property -dict {PACKAGE_PIN E29 IOSTANDARD LVCMOS25} [get_ports {io_chipio_3_cim_fpga_result[1]}]
set_property -dict {PACKAGE_PIN A30 IOSTANDARD LVCMOS25} [get_ports {io_chipio_3_cim_fpga_result[2]}]
set_property -dict {PACKAGE_PIN B30 IOSTANDARD LVCMOS25} [get_ports {io_chipio_3_cim_fpga_result[3]}]
set_property -dict {PACKAGE_PIN C30 IOSTANDARD LVCMOS25} [get_ports {io_chipio_3_cim_fpga_result[4]}]
set_property -dict {PACKAGE_PIN D29 IOSTANDARD LVCMOS25} [get_ports {io_chipio_3_cim_fpga_result[5]}]
set_property -dict {PACKAGE_PIN B29 IOSTANDARD LVCMOS25} [get_ports {io_chipio_3_cim_fpga_result[6]}]
set_property -dict {PACKAGE_PIN C29 IOSTANDARD LVCMOS25} [get_ports {io_chipio_3_cim_fpga_result[7]}]

# chip4 IO bank16
set_property -dict {PACKAGE_PIN C25 IOSTANDARD LVCMOS25} [get_ports  io_chipio_4_cim_fpga_clk]
set_property -dict {PACKAGE_PIN B24 IOSTANDARD LVCMOS25} [get_ports  io_chipio_4_cim_fpga_state]
set_property -dict {PACKAGE_PIN C24 IOSTANDARD LVCMOS25} [get_ports  io_chipio_4_fpga_cim_cmd]
set_property -dict {PACKAGE_PIN A27 IOSTANDARD LVCMOS25} [get_ports {io_chipio_4_fpga_cim_data[0]}]
set_property -dict {PACKAGE_PIN B27 IOSTANDARD LVCMOS25} [get_ports {io_chipio_4_fpga_cim_data[1]}]
set_property -dict {PACKAGE_PIN G24 IOSTANDARD LVCMOS25} [get_ports {io_chipio_4_cim_fpga_result[0]}]
set_property -dict {PACKAGE_PIN G23 IOSTANDARD LVCMOS25} [get_ports {io_chipio_4_cim_fpga_result[1]}]
set_property -dict {PACKAGE_PIN E26 IOSTANDARD LVCMOS25} [get_ports {io_chipio_4_cim_fpga_result[2]}]
set_property -dict {PACKAGE_PIN F26 IOSTANDARD LVCMOS25} [get_ports {io_chipio_4_cim_fpga_result[3]}]
set_property -dict {PACKAGE_PIN D24 IOSTANDARD LVCMOS25} [get_ports {io_chipio_4_cim_fpga_result[4]}]
set_property -dict {PACKAGE_PIN E24 IOSTANDARD LVCMOS25} [get_ports {io_chipio_4_cim_fpga_result[5]}]
set_property -dict {PACKAGE_PIN E25 IOSTANDARD LVCMOS25} [get_ports {io_chipio_4_cim_fpga_result[6]}]
set_property -dict {PACKAGE_PIN F25 IOSTANDARD LVCMOS25} [get_ports {io_chipio_4_cim_fpga_result[7]}]

# chip5 IO bank17  1
set_property -dict {PACKAGE_PIN E19 IOSTANDARD LVCMOS25} [get_ports  io_chipio_5_cim_fpga_clk]
set_property -dict {PACKAGE_PIN B19 IOSTANDARD LVCMOS25} [get_ports  io_chipio_5_cim_fpga_state]
set_property -dict {PACKAGE_PIN C19 IOSTANDARD LVCMOS25} [get_ports  io_chipio_5_fpga_cim_cmd]
set_property -dict {PACKAGE_PIN A22 IOSTANDARD LVCMOS25} [get_ports {io_chipio_5_fpga_cim_data[0]}]
set_property -dict {PACKAGE_PIN B22 IOSTANDARD LVCMOS25} [get_ports {io_chipio_5_fpga_cim_data[1]}]
set_property -dict {PACKAGE_PIN A18 IOSTANDARD LVCMOS25} [get_ports {io_chipio_5_cim_fpga_result[0]}]
set_property -dict {PACKAGE_PIN B18 IOSTANDARD LVCMOS25} [get_ports {io_chipio_5_cim_fpga_result[1]}]
set_property -dict {PACKAGE_PIN A21 IOSTANDARD LVCMOS25} [get_ports {io_chipio_5_cim_fpga_result[2]}]
set_property -dict {PACKAGE_PIN A20 IOSTANDARD LVCMOS25} [get_ports {io_chipio_5_cim_fpga_result[3]}]
set_property -dict {PACKAGE_PIN A17 IOSTANDARD LVCMOS25} [get_ports {io_chipio_5_cim_fpga_result[4]}]
set_property -dict {PACKAGE_PIN A16 IOSTANDARD LVCMOS25} [get_ports {io_chipio_5_cim_fpga_result[5]}]
set_property -dict {PACKAGE_PIN B20 IOSTANDARD LVCMOS25} [get_ports {io_chipio_5_cim_fpga_result[6]}]
set_property -dict {PACKAGE_PIN C20 IOSTANDARD LVCMOS25} [get_ports {io_chipio_5_cim_fpga_result[7]}]

# chip6 IO bank17  2
set_property -dict {PACKAGE_PIN D17 IOSTANDARD LVCMOS25} [get_ports  io_chipio_6_cim_fpga_clk]
set_property -dict {PACKAGE_PIN C22 IOSTANDARD LVCMOS25} [get_ports  io_chipio_6_cim_fpga_state]
set_property -dict {PACKAGE_PIN D22 IOSTANDARD LVCMOS25} [get_ports  io_chipio_6_fpga_cim_cmd]
set_property -dict {PACKAGE_PIN F22 IOSTANDARD LVCMOS25} [get_ports {io_chipio_6_fpga_cim_data[0]}]
set_property -dict {PACKAGE_PIN G22 IOSTANDARD LVCMOS25} [get_ports {io_chipio_6_fpga_cim_data[1]}]
set_property -dict {PACKAGE_PIN F17 IOSTANDARD LVCMOS25} [get_ports {io_chipio_6_cim_fpga_result[0]}]
set_property -dict {PACKAGE_PIN G17 IOSTANDARD LVCMOS25} [get_ports {io_chipio_6_cim_fpga_result[1]}]
set_property -dict {PACKAGE_PIN B17 IOSTANDARD LVCMOS25} [get_ports {io_chipio_6_cim_fpga_result[2]}]
set_property -dict {PACKAGE_PIN C17 IOSTANDARD LVCMOS25} [get_ports {io_chipio_6_cim_fpga_result[3]}]
set_property -dict {PACKAGE_PIN F18 IOSTANDARD LVCMOS25} [get_ports {io_chipio_6_cim_fpga_result[4]}]
set_property -dict {PACKAGE_PIN G18 IOSTANDARD LVCMOS25} [get_ports {io_chipio_6_cim_fpga_result[5]}]
set_property -dict {PACKAGE_PIN C16 IOSTANDARD LVCMOS25} [get_ports {io_chipio_6_cim_fpga_result[6]}]
set_property -dict {PACKAGE_PIN D16 IOSTANDARD LVCMOS25} [get_ports {io_chipio_6_cim_fpga_result[7]}]

# chip7 IO bank17  3
set_property -dict {PACKAGE_PIN F20 IOSTANDARD LVCMOS25} [get_ports  io_chipio_7_cim_fpga_clk]
set_property -dict {PACKAGE_PIN C21 IOSTANDARD LVCMOS25} [get_ports  io_chipio_7_cim_fpga_state]
set_property -dict {PACKAGE_PIN D21 IOSTANDARD LVCMOS25} [get_ports  io_chipio_7_fpga_cim_cmd]
set_property -dict {PACKAGE_PIN H22 IOSTANDARD LVCMOS25} [get_ports {io_chipio_7_fpga_cim_data[0]}]
set_property -dict {PACKAGE_PIN H21 IOSTANDARD LVCMOS25} [get_ports {io_chipio_7_fpga_cim_data[1]}]
set_property -dict {PACKAGE_PIN K20 IOSTANDARD LVCMOS25} [get_ports {io_chipio_7_cim_fpga_result[0]}]
set_property -dict {PACKAGE_PIN K19 IOSTANDARD LVCMOS25} [get_ports {io_chipio_7_cim_fpga_result[1]}]
set_property -dict {PACKAGE_PIN L18 IOSTANDARD LVCMOS25} [get_ports {io_chipio_7_cim_fpga_result[2]}]
set_property -dict {PACKAGE_PIN L17 IOSTANDARD LVCMOS25} [get_ports {io_chipio_7_cim_fpga_result[3]}]
set_property -dict {PACKAGE_PIN H19 IOSTANDARD LVCMOS25} [get_ports {io_chipio_7_cim_fpga_result[4]}]
set_property -dict {PACKAGE_PIN J19 IOSTANDARD LVCMOS25} [get_ports {io_chipio_7_cim_fpga_result[5]}]
set_property -dict {PACKAGE_PIN H17 IOSTANDARD LVCMOS25} [get_ports {io_chipio_7_cim_fpga_result[6]}]
set_property -dict {PACKAGE_PIN J17 IOSTANDARD LVCMOS25} [get_ports {io_chipio_7_cim_fpga_result[7]}]

# chip8 IO bank18  1
set_property -dict {PACKAGE_PIN G13 IOSTANDARD LVCMOS25} [get_ports  io_chipio_8_cim_fpga_clk]
set_property -dict {PACKAGE_PIN A15 IOSTANDARD LVCMOS25} [get_ports  io_chipio_8_cim_fpga_state]
set_property -dict {PACKAGE_PIN B14 IOSTANDARD LVCMOS25} [get_ports  io_chipio_8_fpga_cim_cmd]
set_property -dict {PACKAGE_PIN B15 IOSTANDARD LVCMOS25} [get_ports {io_chipio_8_fpga_cim_data[0]}]
set_property -dict {PACKAGE_PIN C15 IOSTANDARD LVCMOS25} [get_ports {io_chipio_8_fpga_cim_data[1]}]
set_property -dict {PACKAGE_PIN A13 IOSTANDARD LVCMOS25} [get_ports {io_chipio_8_cim_fpga_result[0]}]
set_property -dict {PACKAGE_PIN B13 IOSTANDARD LVCMOS25} [get_ports {io_chipio_8_cim_fpga_result[1]}]
set_property -dict {PACKAGE_PIN C14 IOSTANDARD LVCMOS25} [get_ports {io_chipio_8_cim_fpga_result[2]}]
set_property -dict {PACKAGE_PIN D14 IOSTANDARD LVCMOS25} [get_ports {io_chipio_8_cim_fpga_result[3]}]
set_property -dict {PACKAGE_PIN E15 IOSTANDARD LVCMOS25} [get_ports {io_chipio_8_cim_fpga_result[4]}]
set_property -dict {PACKAGE_PIN E14 IOSTANDARD LVCMOS25} [get_ports {io_chipio_8_cim_fpga_result[5]}]
set_property -dict {PACKAGE_PIN E16 IOSTANDARD LVCMOS25} [get_ports {io_chipio_8_cim_fpga_result[6]}]
set_property -dict {PACKAGE_PIN F15 IOSTANDARD LVCMOS25} [get_ports {io_chipio_8_cim_fpga_result[7]}]

# chip9 IO bank18  2
set_property -dict {PACKAGE_PIN H14 IOSTANDARD LVCMOS25} [get_ports  io_chipio_9_cim_fpga_clk]
set_property -dict {PACKAGE_PIN H12 IOSTANDARD LVCMOS25} [get_ports  io_chipio_9_cim_fpga_state]
set_property -dict {PACKAGE_PIN H11 IOSTANDARD LVCMOS25} [get_ports  io_chipio_9_fpga_cim_cmd]
set_property -dict {PACKAGE_PIN H16 IOSTANDARD LVCMOS25} [get_ports {io_chipio_9_fpga_cim_data[0]}]
set_property -dict {PACKAGE_PIN J16 IOSTANDARD LVCMOS25} [get_ports {io_chipio_9_fpga_cim_data[1]}]
set_property -dict {PACKAGE_PIN C11 IOSTANDARD LVCMOS25} [get_ports {io_chipio_9_cim_fpga_result[0]}]
set_property -dict {PACKAGE_PIN D11 IOSTANDARD LVCMOS25} [get_ports {io_chipio_9_cim_fpga_result[1]}]
set_property -dict {PACKAGE_PIN A12 IOSTANDARD LVCMOS25} [get_ports {io_chipio_9_cim_fpga_result[2]}]
set_property -dict {PACKAGE_PIN A11 IOSTANDARD LVCMOS25} [get_ports {io_chipio_9_cim_fpga_result[3]}]
set_property -dict {PACKAGE_PIN E11 IOSTANDARD LVCMOS25} [get_ports {io_chipio_9_cim_fpga_result[4]}]
set_property -dict {PACKAGE_PIN F11 IOSTANDARD LVCMOS25} [get_ports {io_chipio_9_cim_fpga_result[5]}]
set_property -dict {PACKAGE_PIN B12 IOSTANDARD LVCMOS25} [get_ports {io_chipio_9_cim_fpga_result[6]}]
set_property -dict {PACKAGE_PIN C12 IOSTANDARD LVCMOS25} [get_ports {io_chipio_9_cim_fpga_result[7]}]

# chip10 IO bank13 1 
set_property -dict {PACKAGE_PIN AE28 IOSTANDARD LVCMOS25} [get_ports  io_chipio_10_cim_fpga_clk]
set_property -dict {PACKAGE_PIN AK26 IOSTANDARD LVCMOS25} [get_ports  io_chipio_10_cim_fpga_state]
set_property -dict {PACKAGE_PIN AJ26 IOSTANDARD LVCMOS25} [get_ports  io_chipio_10_fpga_cim_cmd]
set_property -dict {PACKAGE_PIN AF27 IOSTANDARD LVCMOS25} [get_ports {io_chipio_10_fpga_cim_data[0]}]
set_property -dict {PACKAGE_PIN AF26 IOSTANDARD LVCMOS25} [get_ports {io_chipio_10_fpga_cim_data[1]}]
set_property -dict {PACKAGE_PIN AH27 IOSTANDARD LVCMOS25} [get_ports {io_chipio_10_cim_fpga_result[0]}]
set_property -dict {PACKAGE_PIN AH26 IOSTANDARD LVCMOS25} [get_ports {io_chipio_10_cim_fpga_result[1]}]
set_property -dict {PACKAGE_PIN AG28 IOSTANDARD LVCMOS25} [get_ports {io_chipio_10_cim_fpga_result[2]}]
set_property -dict {PACKAGE_PIN AG27 IOSTANDARD LVCMOS25} [get_ports {io_chipio_10_cim_fpga_result[3]}]
set_property -dict {PACKAGE_PIN AK28 IOSTANDARD LVCMOS25} [get_ports {io_chipio_10_cim_fpga_result[4]}]
set_property -dict {PACKAGE_PIN AJ27 IOSTANDARD LVCMOS25} [get_ports {io_chipio_10_cim_fpga_result[5]}]
set_property -dict {PACKAGE_PIN AD26 IOSTANDARD LVCMOS25} [get_ports {io_chipio_10_cim_fpga_result[6]}]
set_property -dict {PACKAGE_PIN AC26 IOSTANDARD LVCMOS25} [get_ports {io_chipio_10_cim_fpga_result[7]}]

# chip11 IO bank13 2 
set_property -dict {PACKAGE_PIN AG29 IOSTANDARD LVCMOS25} [get_ports  io_chipio_11_cim_fpga_clk]
set_property -dict {PACKAGE_PIN AB30 IOSTANDARD LVCMOS25} [get_ports  io_chipio_11_cim_fpga_state]
set_property -dict {PACKAGE_PIN AB29 IOSTANDARD LVCMOS25} [get_ports  io_chipio_11_fpga_cim_cmd]
set_property -dict {PACKAGE_PIN AE29 IOSTANDARD LVCMOS25} [get_ports {io_chipio_11_fpga_cim_data[0]}]
set_property -dict {PACKAGE_PIN AD29 IOSTANDARD LVCMOS25} [get_ports {io_chipio_11_fpga_cim_data[1]}]
set_property -dict {PACKAGE_PIN AH30 IOSTANDARD LVCMOS25} [get_ports {io_chipio_11_cim_fpga_result[0]}]
set_property -dict {PACKAGE_PIN AG30 IOSTANDARD LVCMOS25} [get_ports {io_chipio_11_cim_fpga_result[1]}]
set_property -dict {PACKAGE_PIN AJ29 IOSTANDARD LVCMOS25} [get_ports {io_chipio_11_cim_fpga_result[2]}]
set_property -dict {PACKAGE_PIN AJ28 IOSTANDARD LVCMOS25} [get_ports {io_chipio_11_cim_fpga_result[3]}]
set_property -dict {PACKAGE_PIN AF30 IOSTANDARD LVCMOS25} [get_ports {io_chipio_11_cim_fpga_result[4]}]
set_property -dict {PACKAGE_PIN AE30 IOSTANDARD LVCMOS25} [get_ports {io_chipio_11_cim_fpga_result[5]}]
set_property -dict {PACKAGE_PIN AK30 IOSTANDARD LVCMOS25} [get_ports {io_chipio_11_cim_fpga_result[6]}]
set_property -dict {PACKAGE_PIN AK29 IOSTANDARD LVCMOS25} [get_ports {io_chipio_11_cim_fpga_result[7]}]

# chip12 IO bank13 3
set_property -dict {PACKAGE_PIN AB27 IOSTANDARD LVCMOS25} [get_ports  io_chipio_12_cim_fpga_clk]
set_property -dict {PACKAGE_PIN AA30 IOSTANDARD LVCMOS25} [get_ports  io_chipio_12_cim_fpga_state]
set_property -dict {PACKAGE_PIN Y30	 IOSTANDARD LVCMOS25} [get_ports  io_chipio_12_fpga_cim_cmd]
set_property -dict {PACKAGE_PIN AC30 IOSTANDARD LVCMOS25} [get_ports {io_chipio_12_fpga_cim_data[0]}]
set_property -dict {PACKAGE_PIN AC29 IOSTANDARD LVCMOS25} [get_ports {io_chipio_12_fpga_cim_data[1]}]
set_property -dict {PACKAGE_PIN AB25 IOSTANDARD LVCMOS25} [get_ports {io_chipio_12_cim_fpga_result[0]}]
set_property -dict {PACKAGE_PIN AA25 IOSTANDARD LVCMOS25} [get_ports {io_chipio_12_cim_fpga_result[1]}]
set_property -dict {PACKAGE_PIN AB28 IOSTANDARD LVCMOS25} [get_ports {io_chipio_12_cim_fpga_result[2]}]
set_property -dict {PACKAGE_PIN AA27 IOSTANDARD LVCMOS25} [get_ports {io_chipio_12_cim_fpga_result[3]}]
set_property -dict {PACKAGE_PIN Y29	 IOSTANDARD LVCMOS25} [get_ports {io_chipio_12_cim_fpga_result[4]}]
set_property -dict {PACKAGE_PIN W29	 IOSTANDARD LVCMOS25} [get_ports {io_chipio_12_cim_fpga_result[5]}]
set_property -dict {PACKAGE_PIN AA28 IOSTANDARD LVCMOS25} [get_ports {io_chipio_12_cim_fpga_result[6]}]
set_property -dict {PACKAGE_PIN Y28	 IOSTANDARD LVCMOS25} [get_ports {io_chipio_12_cim_fpga_result[7]}]

# chip13 IO bank12 1
set_property -dict {PACKAGE_PIN AG24 IOSTANDARD LVCMOS25} [get_ports  io_chipio_13_cim_fpga_clk]
set_property -dict {PACKAGE_PIN AH22 IOSTANDARD LVCMOS25} [get_ports  io_chipio_13_cim_fpga_state]
set_property -dict {PACKAGE_PIN AG22 IOSTANDARD LVCMOS25} [get_ports  io_chipio_13_fpga_cim_cmd]
set_property -dict {PACKAGE_PIN AF21 IOSTANDARD LVCMOS25} [get_ports {io_chipio_13_fpga_cim_data[0]}]
set_property -dict {PACKAGE_PIN AF20 IOSTANDARD LVCMOS25} [get_ports {io_chipio_13_fpga_cim_data[1]}]
set_property -dict {PACKAGE_PIN AH25 IOSTANDARD LVCMOS25} [get_ports {io_chipio_13_cim_fpga_result[0]}]
set_property -dict {PACKAGE_PIN AG25 IOSTANDARD LVCMOS25} [get_ports {io_chipio_13_cim_fpga_result[1]}]
set_property -dict {PACKAGE_PIN AK24 IOSTANDARD LVCMOS25} [get_ports {io_chipio_13_cim_fpga_result[2]}]
set_property -dict {PACKAGE_PIN AK23 IOSTANDARD LVCMOS25} [get_ports {io_chipio_13_cim_fpga_result[3]}]
set_property -dict {PACKAGE_PIN AF25 IOSTANDARD LVCMOS25} [get_ports {io_chipio_13_cim_fpga_result[4]}]
set_property -dict {PACKAGE_PIN AE25 IOSTANDARD LVCMOS25} [get_ports {io_chipio_13_cim_fpga_result[5]}]
set_property -dict {PACKAGE_PIN AK25 IOSTANDARD LVCMOS25} [get_ports {io_chipio_13_cim_fpga_result[6]}]
set_property -dict {PACKAGE_PIN AJ24 IOSTANDARD LVCMOS25} [get_ports {io_chipio_13_cim_fpga_result[7]}]

# chip14 IO bank12 2
set_property -dict {PACKAGE_PIN AF22 IOSTANDARD LVCMOS25} [get_ports  io_chipio_14_cim_fpga_clk]
set_property -dict {PACKAGE_PIN AE21 IOSTANDARD LVCMOS25} [get_ports  io_chipio_14_cim_fpga_state]
set_property -dict {PACKAGE_PIN AD21 IOSTANDARD LVCMOS25} [get_ports  io_chipio_14_fpga_cim_cmd]
set_property -dict {PACKAGE_PIN AD24 IOSTANDARD LVCMOS25} [get_ports {io_chipio_14_fpga_cim_data[0]}]
set_property -dict {PACKAGE_PIN AC24 IOSTANDARD LVCMOS25} [get_ports {io_chipio_14_fpga_cim_data[1]}]
set_property -dict {PACKAGE_PIN AD22 IOSTANDARD LVCMOS25} [get_ports {io_chipio_14_cim_fpga_result[0]}]
set_property -dict {PACKAGE_PIN AC22 IOSTANDARD LVCMOS25} [get_ports {io_chipio_14_cim_fpga_result[1]}]
set_property -dict {PACKAGE_PIN AC25 IOSTANDARD LVCMOS25} [get_ports {io_chipio_14_cim_fpga_result[2]}]
set_property -dict {PACKAGE_PIN AB24 IOSTANDARD LVCMOS25} [get_ports {io_chipio_14_cim_fpga_result[3]}]
set_property -dict {PACKAGE_PIN AB20 IOSTANDARD LVCMOS25} [get_ports {io_chipio_14_cim_fpga_result[4]}]
set_property -dict {PACKAGE_PIN AA20 IOSTANDARD LVCMOS25} [get_ports {io_chipio_14_cim_fpga_result[5]}]
set_property -dict {PACKAGE_PIN AC21 IOSTANDARD LVCMOS25} [get_ports {io_chipio_14_cim_fpga_result[6]}]
set_property -dict {PACKAGE_PIN AC20 IOSTANDARD LVCMOS25} [get_ports {io_chipio_14_cim_fpga_result[7]}]

# chip15 IO bank12 3
set_property -dict {PACKAGE_PIN AD23 IOSTANDARD LVCMOS25} [get_ports  io_chipio_15_cim_fpga_clk]
set_property -dict {PACKAGE_PIN AH24 IOSTANDARD LVCMOS25} [get_ports  io_chipio_15_cim_fpga_state]
set_property -dict {PACKAGE_PIN AG23 IOSTANDARD LVCMOS25} [get_ports  io_chipio_15_fpga_cim_cmd]
set_property -dict {PACKAGE_PIN AE24 IOSTANDARD LVCMOS25} [get_ports {io_chipio_15_fpga_cim_data[0]}]
set_property -dict {PACKAGE_PIN AF23 IOSTANDARD LVCMOS25} [get_ports {io_chipio_15_fpga_cim_data[1]}]
set_property -dict {PACKAGE_PIN AA23 IOSTANDARD LVCMOS25} [get_ports {io_chipio_15_cim_fpga_result[0]}]
set_property -dict {PACKAGE_PIN AA22 IOSTANDARD LVCMOS25} [get_ports {io_chipio_15_cim_fpga_result[1]}]
set_property -dict {PACKAGE_PIN AB23 IOSTANDARD LVCMOS25} [get_ports {io_chipio_15_cim_fpga_result[2]}]
set_property -dict {PACKAGE_PIN AB22 IOSTANDARD LVCMOS25} [get_ports {io_chipio_15_cim_fpga_result[3]}]
set_property -dict {PACKAGE_PIN AA21 IOSTANDARD LVCMOS25} [get_ports {io_chipio_15_cim_fpga_result[4]}]
set_property -dict {PACKAGE_PIN Y21 IOSTANDARD LVCMOS25} [get_ports {io_chipio_15_cim_fpga_result[5]}]
set_property -dict {PACKAGE_PIN Y24 IOSTANDARD LVCMOS25} [get_ports {io_chipio_15_cim_fpga_result[6]}]
set_property -dict {PACKAGE_PIN Y23 IOSTANDARD LVCMOS25} [get_ports {io_chipio_15_cim_fpga_result[7]}]

